#  Simulation Model Generator
#  Xilinx EDK 14.4 EDK_P.49d
#  Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
#
#  File     top_level_ports_wave.tcl (Wed May 22 15:07:26 2013)
#
if { [info exists PathSeparator] } { set ps $PathSeparator } else { set ps "/" }
if { ![info exists tbpath] } { set tbpath "${ps}system" }

wave add $tbpath${ps}fpga_0_RS232_Uart_1_RX_pin -into $id 
wave add $tbpath${ps}fpga_0_RS232_Uart_1_TX_pin -into $id 
wave add $tbpath${ps}fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin -into $id 
wave add $tbpath${ps}fpga_0_LEDs_8Bits_GPIO_IO_O_pin -into $id 
wave add $tbpath${ps}fpga_0_Push_Buttons_4Bits_GPIO_IO_I_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_MEM_ADDR_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_DQ_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_MEM_OEN_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_MEM_WEN_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_RAM_CEN_O_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_RAM_BEN_O_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_FLASH_ADDR_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_FLASH_CEN_O_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_FLASH_RPN_O_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_QUAD_SPI_C_O_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_QUAD_SPI_S_O_pin -into $id 
wave add $tbpath${ps}fpga_0_mem_bus_mux_0_MOSI_QUAD_SPI_pin -into $id 
wave add $tbpath${ps}fpga_0_clk_1_sys_clk_pin -into $id 
wave add $tbpath${ps}fpga_0_rst_1_sys_rst_pin -into $id 

